What Are Vias And Why Do You Need Them?

Just as a printed circuit board (PCB) is a means to allow interconnection of different components, vias are means to interconnect different layers on and within the multilayered PCBs. Also, just like there are various types of PCBs, there are multiple types of vias with their own functionality. Simply put, vias are Plated-Through Holes (PTHs) passing through one or more layers in a PCB, connecting traces on its way. IPC defines seven types of vias in IPC-50M, Terms and Definitions for Interconnecting and Packaging Electronic Circuits. These are:

Type I: Tented Vias—vias that have a mask material applied, bridging over them, with no additional material inside the holes.

Type II: Tented and Covered Vias—type I vias with a secondary covering of mask material over and above the tented vias.

Type III: Plugged Vias—vias with material partly penetrating into the via holes.

Type IV: Plugged and Covered Vias—type III vias with a secondary material covering the vias.

Type V: Filled Vias—vias with material fully penetrating and encapsulating the via holes.

Type VI: Filled and Covered—type V vias with a secondary material covering the vias.

Type VII: Filled and Capped—type V vias with a secondary metalized coating covering the vias.

                                                            Fig. 1: Close-up of a Via

Although small and sometimes very small, vias are extremely important parts of the circuit board landscape. In fact, in the world of surface mount components, vias are the only means to interconnect copper traces on different layers on a PCB, where earlier, leads of components would do the job when soldered on both sides of a two-layer PCB. The only difference between plated-through holes and vias is no component lead will ever pass through the hole of a via.

                                                        Fig. 2: Different Types of Vias

Each of the seven types of vias classified above may be further subdivided into three types depending on their functionality—blind or hidden vias, buried vias, and through hole vias. As the name suggests, through hole vias travel through the board, connecting traces on the outermost layers, and if required, on the inner layers as well. Blind vias start on the surface on one side of the board, but do not extend to the other side, finishing on one of the internal layers instead. Buried vias remain completely encapsulated within the board, and none of their ends extend to any of the outer surfaces of the board.

Most vias in high-density boards have very small-diameter holes, and are called micro-vias. Manufacturers use different tools such as ultrasonic beams and lasers to drill these holes. Usually, micro-vias are filled with a conductive material to facilitate connecting with the pad on the other layer. However, this can lead to issues with unequal expansion as explained later.

Tented Vias

                                                                  Fig. 3: Tented Vias

The word “tenting” in the PCB industry originally meant the solder mask would enclose the via fully in the form of a skin or tent over the hole. This was difficult for manufacturers to achieve with liquid photo-imageable (LPI) solder mask, as the success of the process was dependent on the diameter of the hole and surface tension of the LPI. With the introduction of dry film solder mask, manufacturers achieved tenting easily, but the process was more expensive.

With LPI, tenting caused the mask to cover the pad and enter the hole partly. However, this was not consistent, as some vias remained unplugged, and others had the tent broken over the hole, covering only the annular ring or pad. Therefore, as per requirement, manufacturers resorted to plugging vias with conductive or non-conductive materials before tenting with LPI.

Tenting is useful for reducing the number of exposed conductive pads present on the PCB, and helps in reducing the likelihood of shorts from solder bridging during the assembly process. In the case of SMT pads, tenting helps to reduce paste migration away from the pads of SMD components when vias are placed either on the ends of their pads or on the dog-bones meant for BGAs.

Additionally, tenting is helpful whenever vias are placed close to SMT pads, especially in areas within the BGA package, where shorts can easily happen under the component during reflow, making rework difficult and time-consuming. Covering the tented via with a secondary coating of solder mask often helps,

Disadvantages of Incomplete Tenting

                                                             Fig. 4: Incomplete Tenting

Although tenting of vias by primary LPI solder mask is advantageous as it is only a single step process, the process cannot guarantee complete tenting, resulting in long-term reliability issues. Successful tenting by screen coating depends on the size of the hole, surface tension of the liquid mask, and the board thickness. As no surface finish is applied to the via barrel before tenting, incomplete tenting may cause entrapments. Usually, this is chemical entrapment from preclean lines when enhancing surface finish.

Preclean lines subject surface finishes to a micro-etching process, allowing micro-etchants to be trapped in the open vias, where the chemical crystallizes rapidly to generate copper-sulfate crystals. Over time, these crystals etch away the copper in the barrel, causing long-term reliability issues. For instance, the gold of the ENIG finish could form a galvanic cell with the exposed copper near the top of the via in the presence of the micro-etchant chemical, thereby accelerating the process of etching.

Incomplete tenting may also cause solder paste to wick into the via, leaving insufficient paste to complete the actual soldering. In the case of BGAs, localized thermal energy may cause the LPI solder mask to lift between the ball and the via capture pads, as the distance between them is very short, causing solder shorts.

Above issues with incomplete tenting has led to manufacturers plugging vias with solder mask or some other non-conductive or even conductive materials. The plugged via does not require surface finish to be applied to the via barrel, but does ensure that subsequent application of the LPI mask leaves all the vias fully tented.

Vias Plugged with Non-Conductive Fill

For vias plugged with solder mask or similar non-conductive epoxy material, the manufacturer has to ensure the via is completely plugged and sealed, and its annular ring is fully covered. This is a common practice when using BGA SMD pads to prevent solder wicking into the via creating poor or non-existent solder joints.

                                                               Fig. 5: Active Pad

However, with BGA packages becoming tighter, it is becoming increasingly difficult placing vias on standard ‘dog-bone’ land patterns for transferring signals to other layers. This difficulty has led to vias being drilled directly into the pads of the BGA footprint. The process is known as via-in-pad, and allows much simpler routing. Although this requires the via hole to be fully plugged, it also requires the surface of the plugged via to be plated over with copper, and subsequently flattened and planarized to be even with the surrounding copper features. Therefore, with the application of the final finish, there is a solderable surface mount pad, also called an active pad, capable of passing signals to inner layers, eliminating the need to place vias on the surface layer for the purpose.

Vias Plugged with Conductive Fill

Some chips generate a lot of heat, which must be conducted away to prevent the chip from overheating. Placing thermal vias plugged with conductive fill under the chip helps in the process, as the metallic nature of the fill naturally wicks the heat away from the chip to the other side of the board, just as a radiator does. This technique is helpful even in cases where a chip draws high currents, as multiple vias plugged with conductive fill reduce the resistance of the track, thereby lowering the voltage drop between the voltage source and the pins of the chip.

Drawbacks of Conductive Fills

Vias filled with conductive fill generally present a different coefficient of thermal expansion (CTE) between the surrounding laminate and the metallic fill. With heat, metals expand much more rapidly than the surrounding laminate does, leading to a possible fracture between the pads and the hole wall. Therefore, where the purpose of the fill is only to reinforce the copper pad plated over the hole, designers using via-in-pad do not recommend the conductive filling process.

Conclusion

Designers often try to match the CTE of the conductive fill for vias with that of the surrounding material. This is important in the view of the board living out its life in a heating/cooling state, where the expansion and contraction of the materials can lead to stress fractures in vias and possible electrical opens in the worst cases. However, this consideration generally favors the non-conductive epoxies for via filling as their CTE matches that of the laminate more closely, making the PCB a more reliable product.

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Trends in Surface Mount Technology and Its Relevance with PCB Surface Finish

It is necessary to mass-produce electronic circuit boards in a highly mechanical manner for ensuring the lowest cost of manufacturing. Traditional through-hole electronic components with leads did not lend themselves to this approach. Therefore, since the 1980s, virtually all electronics hardware is being mass-produced using surface mount technology (SMT). Compared to the through-hole technology (THT) used earlier, the surface mount devices (SMD) associated with SMT offer several advantages in terms of manufacturability and performance.

Trends in Surface Mount Packaging

Almost all electronic components are available in forms suitable for surface mounting. SMDs do not have long leads that necessitates passing through the printed circuit board (PCB). Rather, they have very short leads that can be soldered directly to the copper pads on the PCB. Manufacturers use different types of SMD packaging, with the evolution tending towards increasing package and pin densities.

                                               Fig. 1: Trends in Surface Mount Packaging

The popular dual in line (DIP) packaging for ICs with two rows of pins for soldering has now diverged into the PGA, QFP, and TSOP type SMD packages. Compared to DIP, these packages have improved on the packaging density enormously. However, modern electronic equipment design demands even higher densities. As a consequence, we now see extremely dense SMD packaging in the form of BGAs, LQFPs, and TCPs. Now, SMD packages are converging towards chip scale packaging (CSP) types, offering better heat dissipation, higher package densities, and increased flexibility.

This trend towards miniaturization is visible for other passive components as well. All types of resistors, capacitors, and inductors are now available in small SMD packages. For instance, although the 0603 and 0402 packages are most commonly used, smaller sizes of 0201 are also available.

Trends in Soldering Techniques for SMT

Most countries have realized the hazards of using the element Lead in electronic equipment, and as a result, the use of lead and tin combination for production and use of solder has almost stopped. Instead, the industry now uses various forms of lead-free solder, although these have more stringent process requirements.

With the advent of new types of SMD packages, the trend in soldering techniques is also evolving. From the commonly used wave soldering for through-hole devices, the trend is towards use of non-contact soldering using infrared and hot gas reflow methods for SMDs.

Trends in Machinery for SMT

Mass production and high mechanization has replaced manual insertion of through-hole components with sophisticated pick-and-place machines for SMD components. These take the form of precision nozzles, intelligent feeder systems, multi-functional mounters, and 3-D molded interconnect devices.

Apart from advances in automated machinery used for SMT, the introduction of special SMD packages such as BGAs has necessitated use of specialized equipment for inspection of PCBs after assembly. Since it is visually impossible to inspect the underside of a BGA chip after it has been soldered, it is necessary to use X-rays to inspect the soldering. With high volumes of production and miniaturization, it is nearly impossible to inspect PCBs manually after assembly. Therefore, the current trend is towards in-circuit testers (ICT) and computerized automated test equipment using high-resolution digital cameras and special algorithms.

Relevance of Surface Finish of PCBs with SMT

The solderable surfaces of a PCB need protection from oxidation while the PCB moves from manufacturing to assembly. Oxidization of the copper surface prevents formation of a good solder joint. Quality of the surface finish affects first pass yield (FPY) and the final product reliability. Primary reasons for this involve non-uniform surface finish and poor solderability. Although there are other known factors for poor FPY, but surface finish issues are the main.

Typical surface finishes manufacturers use are:

• Hot Air Solder Leveling (HASL)
• Organic Solderability Preservatives (OSP)
• Immersion Silver (ImAg)
• Immersion Tin (ImSn)
• Electroless Nickel/Immersion Gold (ENIG)
• Electroless Nickel Electroless Palladium Immersion Gold (ENEPIG)

Hot Air Solder Leveling (HASL) is the most common PCB finish, for both lead and lead-free compositions of solder. The process involves application of molten solder to the exposed pads in a vertical or horizontal panel orientation, with excess solder being blown away with a forced hot air knife. The typical thickness of HASL solder on the copper pad ranges from 0.3-1.5 mil, melting at 183°C for lead solder and at 228°C for lead-free solder, with a typical 12-month shelf life.

                                                      Fig. 2: Hot Air Solder Leveling

However, for HDI applications, the HASL process presents a highly variable topography, or inconsistent surface planarity because of the formation of solder beads/balls not conducive to SMT, especially for QFP and BGA packages. In addition, depending on the alloy used for lead-free solder, the HASL process may be aggressive on copper, reducing the shelf life. While the thermal shock may cause warping of the PCB, there can be PTH diameter issues and bridging of fine pitch traces with solder mask residue preventing HASL from flowing. In addition, contamination on the surface of the copper or resin residue on the laminate may cause poor bonding.

Organic Solderability Preservatives (OSP) is a low-cost transparent coating of organic material, which preserves the copper surface from oxidation until assembly. The process involves application in a dip tank with the PCB in a vertical position, or the use of a conveyorized chemical process, which leaves a very thin coating of the material, typically 100-4000 Angstroms thick. Although OSP is a flat, reliable planar surface, well suited to BGA and QFP packages, the shelf life is rather low, being typically 6 months or lower.

                                              Fig. 3: Organic Solderability Preservatives

OSP is difficult to inspect, and does not stand multiple reflows very well. This raises questions of reliability of exposed copper pads after assembly. As OSP is not conductive, ICT test pads need to be soldered.

Immersion Silver (ImAg) is a metallic solderability preservative, and the process deposits 8-15 micro inches of nearly pure silver on the copper surface. Although it provides a flat, planar surface, excellent solderability, and about 6-12 months of shelf life, immersion silver is sensitive to handling, packaging, electrical tests, and suffers from creep corrosion from salt and sulfur in the environment.

                                                            Fig. 4: Immersion Silver

Immersion Tin (ImSn) forms an intermetallic joint with copper to provide a uniform, dense coating with excellent hole-wall lubricity. As it is possible to engineer immersion tin to be non-porous and with very fine grain, it is the top choice for backplane panel assemblies requiring press-fit pin insertions.

However, immersion tin has a shelf life of 6 months, and is sensitive to handling. In addition, processing of immersion tin requires using Thiourea, a carcinogen with environmental issues.

                                                               Fig. 5: Immersion Tin

Electroless Nickel Immersion Gold (ENIG) is a complicated chemical process, involving nickel plating over the copper pad and subsequent gold plating over the nickel. The gold layer prevents the nickel from oxidizing during storage, while also providing low contact resistance, good wetting for solder, and excellent shelf life of typically 12 months. The flat planar surface is well suited for fine pitch devices such as BGA and QFP. Being conductive, ENIG offers good ICT contacts.

                                              Fig. 6: Electroless Nickel Immersion Gold

However, ENIG is an expensive process, with non-wetting issues if the process has not been executed properly. Slow intermetallic growth can result in poor joint reliability and strength.

Electroless Nickel Electroless Palladium immersion Gold (ENEPIG) is another complicated chemical process, involving depositing electroless nickel on the copper surface, followed by a coating of electroless palladium layer, topped with a layer of immersion gold. The triple layer helps to form a superior solder joint with lead-free solder. As the process allows a thinner layer of gold, the process is less expensive when compared to ENIG, although the extra process step offsets this. The flat planar surface suits fine pitch devices such as BGA and QFPs. As the shelf life is typically 12 months, ENEPIG is the fastest growing surface finish.

                            Fig. 7: Electroless Nickel Electroless Palladium Immersion Gold

Conclusion

PCB manufacturers prefer ENIG and ENEPIG to others because of the relative advantages the two techniques offer, although between the two, their advantages vary. ENIG is suitable for SMT, especially for BGA and other fine pitch components. The technology works well for lead-free soldering, and is highly reliable, which is why the flex PCB market prefers ENIG.

On the other hand, ENEPIG has a much wider acceptance and is suitable for multiple types of packages including THT, SMT, wire bonding, press fit, and more. Apart from being suitable for fine-pitch SMD components such as BGA and QFPs, ENEPIG is applicable to PCBs with different manufacturing technologies, requiring higher densities and reliability.

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RF Design and High Frequency Board Manufacturing

The performance of a product operating at high frequencies depends largely on the electrical characteristics of the Printed Circuit Board (PCB) used for mounting and connecting its circuit components. The magnitude of the impact of the PCB design increases exponentially with increase of the operational frequency. Therefore, designers need to include electrical models of PCB structures when simulating RF circuits. For achieving optimum solutions, the product/PCB designer and the manufacturing engineer must appreciate the requirements of RF design.

Designing for High Frequencies

Designing a board to work at high frequencies requires the designer to be critical of the following areas:

• Material used for the PCB
• Placement of traces
• Placement of planes
• Component interconnections

Materials Used for RF PCBs

RF PCBs can use a variety of different materials. Although common board materials used for high frequency circuits are FR-4 and derivatives of FR-4, many other base substrates are also used as they offer better electrical performance. These include specialized low-loss RF material such as pure PTFE, ceramic filled PTFE, Hydrocarbon Ceramic, and High-Temperature Thermoplastic/Ceramic.

Although FR-4 has its limitations when used for high-frequency work, the RF designer must understand these limitations and make cost/performance tradeoffs for the design. Typical limitations of FR-4 are:

• Stability of dielectric constant—Varying from lot to lot and over frequency
• Loss factor—Depending on surface contamination and the hygroscopic nature of the material
• Ability to withstand processing temperatures—Lead-free processing temperatures are higher than regular soldering temperatures
• Thermal conductivity—Even low-power RF circuits can produce a lot of heat

Therefore, selecting a suitable material for making a PCB operating at high frequencies depends on the above factors and the product cost. The choice could range from the low-cost FR-4 material, with its higher loss and not tightly controlled dielectric constant, to FR-4 derivatives with better specifications, or to other specialized low-loss RF material with their well-specified dielectric constant.

Fabrication Issues with Special Materials

All laminates mentioned above involve individual fabrication issues. For achieving the proper quality and reliability, the manufacturer must follow these individual fabrication notes for each substrate material for storing, handling, preparing the inner layer, surface preparation for photoresist application, bonding, drilling, deburring, and plating.

Manufacturers require setting up special processes for fabricating PCBs with low-loss RF materials to work at high frequencies. For instance, plated-through hole preparation is very critical for PTFE substrates—it needs an etch-back process requiring Plasma etch setup to prepare the PTFE hole surface and make it capable of accepting electroless copper plating. Therefore, apart from proper selection of material, following the proper fabrication methods is equally important for achieving a good quality PCB working reliably at high frequencies.

Placement of Traces

For matching the impedance, designers effectively manage the spacing of traces, ground planes, and the dielectric material to form a controlled impedance transmission line. They do this in several ways—in the form of a microstrip, stripline, co-planar waveguides, and differential pairs. The width of the trace, the dielectric thickness, dielectric constant of the used dielectric material and copper thickness determine the impedance. As high frequency signals are very sensitive to noise, ringing, and reflections, they must be designed with great care towards impedance. Mostly preferred impedance is 50 ohms for single ended and 100 ohms for differential, with control limits of ±10%.

Fig.1: Microstrip

Fig.2: Centered Stripline

Fig.3: Off-Center

Microstrip: This is a circuit trace carrying the RF signals routed on an outside layer of the PCB with a reference plane below it. The reference plane may be power or ground plane.

Stripline: This is a circuit trace carrying the RF signals routed on an inside layer of the PCB with two low-voltage reference planes above and below it. The reference planes may be power and or ground plane. The stripline can be equidistant from the two reference planes, in which case it is called the centered stripline, or it can be an off-center stripline, where it is closer to one of the reference planes.

Fig.4: Coplanar

Fig.5: Coplanar Waveguide with Ground

Co-planar Waveguide: This is a circuit trace carrying the RF signals embedded within a ground reference plane on the same layer of the PCB. Co-planar waveguides (CPW) offer lower loss tangent than microstrips do, but have a higher skin effect loss, as fields concentrate on the edges of the trace and ground. Another form of co-planar waveguide is the co-planar waveguide with ground (CPWG), where a ground plane is placed just below the waveguide layer.

Fig.6: Coplanar Differential Pair

Fig.7: Coplanar Differential Pair with

Co-planar Differential Pairs: These are two traces carrying the RF signals embedded within a ground reference plane on the same layer of the PCB. This arrangement is also called the CP Differential Pair or Edge-Coupled CPW. This gives an extra degree of signal-to-noise isolation over the standard CPW. An added ground plane just below the layer offers even better field containment over the coupled CPW, and is called the Edge Coupled CPWG.

Placement of Planes

Most RF products use multilayer PCBs. These comprise a number of laminates of the substrate material separately etched, drilled, and bonded. The chief advantage of this is to allow the use of more than two conductor layers, thereby reducing the required board space, but at increased cost.

Setting up the laminates is a major part of the design for a multilayer RF board. The stack defines the number of layers the board will ultimately possess. At this stage, it is important to define the layers carrying specific high-speed tracks, and the placement of the ground and power layers with respect to those layers. Enclosing tracks carrying high frequency signals within the ground and power layers serves to define two significant factors related to high speed multilayer design—minimizing cross-talk, and maintaining a check on the impedance on the board. However, the cost of the board increases proportional to the number of layers it has, and therefore, the number of layers is usually a compromise of the board’s functionality and its cost.

RF products typically use a four or six layer FR-4 multilayer construction. Drilled and plated through holes or vias link tracks on one layer to tracks on other layers or all layers. Complex structures use blind or buried vias, with blind vias connecting the outermost layers to one or more inner ones, while buried vias connect only the inner layers and do not appear on the outermost layers. The third type of via is the through via, going through all the layers of the board. To create the connections, it is necessary to drill and then plate-through all vias. Via structures have a major effect on the fabrication processes of the PCB and contribute to the cost of the finished board.

Component Interconnections

Parasitic elements of a PCB refer to its physical attributes that affect the performance of the circuit. For instance, at high frequencies, a long thin track will usually be inductive, while a large pad over a ground plane will behave like a capacitor. In addition, when modeling in real circuits for, say a series capacitor, the designer must also include the impedance of the connections between the ground plane and circuit components.

A plated through via hole also adds significant inductance. RF designers can use good circuit simulation packages that include models to allow their addition. For instance, the typical inductance of a 0.2 mm diameter, 1.6 mm long hole can be as much as 0.75 nH. Although this may seem to be small, it can exert significant influence at high frequencies.

Components mounted on the PCB also contribute with their non-ideal characteristics. The use of Surface Mount Device (SMD) components helps to reduce the effect largely because of their reduced lead lengths and small construction, but the effect is still prominent at higher frequencies.

Designers use different ground plane strategies for their RF PCB design, and there is no unique solution as the best strategy. While most designers advocate breaking up the ground plane over the analog, digital, radio, and audio parts of the circuit, providing an individual ground plane of low impedance for all parts of the circuit is usually a good point to start.

Designers need to consider the flow of currents carefully throughout the product to minimize interferences between the audio and radio circuits. This assumes even greater significance if the design uses Digital Signal Processing (DSP) and microprocessors.

RF PCB Layout Strategies and Techniques

• Separate all RF, low-level analog,  and digital sections.
• Divide the RF section into circuit groups (amps, LO, VCO, etc.).
• Place all the high-frequency components early in the layout, as this helps to minimize the length of the RF routes (in RF PCBs, functional orientation is more important compared to DFM).
• Place the components carrying the highest frequency next to the connectors.
• Never place unrelated inputs and outputs next to each other. For instance, multi-stage windings should never be placed adjacent.
• When long input or output to RF amplifiers is unavoidable, choose to make the output longer.
• As the trace impedance is a critical factor when trying to control reflections, always match the impedance between the driver and the load, except where the trace is shorter than 1/20th of the wavelength.
• When using pull-up inductors or resistors at the outputs of open-collector devices, always place the pull-up component next to the output pin it is pulling up.
• In addition to decoupling the main power pins of the IC, decouple the pull-up also.
• Inductors usually have large magnetic fields around them-

• Never placed them close together, when in parallel (unless the intention is to couple their magnetic fields)
• Separate all inductors by 1x times the body height (minimum) OR
• Place inductors perpendicular to one another
• Confine “ALL” routes to the section or stage to which they are assigned –
• Digital traces in the digital section
• Low-level analog traces in the low-level analog section
• RF traces in the RF section
• Routing traces into adjoining sections is not recommended
• Route all short RF traces on the component side of the PCB, rout them to eliminate vias
• Place a ground layer below the RF traces.
• Minimize the vias in the RF path, as this reduces the breaks in the ground plane(s) and –
• Minimizes inductance
• Helps contain stray magnetic and electric fields.
• Long controls lines are acceptable, but take care to route them away from RF inputs.
• Keep RF lines away from one another by a minimum distance to avoid unintended coupling & crosstalk.
• Minimum spacing is a function of the acceptable level of coupling, and is good for crosstalk, directional couplers, crosstalk, differential lines coupled in even or odd modes.

Summary

Finally, the design of a PCB and its fabrication for high frequency use is a complex process requiring intimate communication between the designer and the fabricator, with each understanding the issues related to high-speed design.

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Important Considerations While Designing A Multi-Layer Board

Apart from the regular Design Rule Checks (DRC) that most Printed Circuit Board (PCB) design software offer and the various standards that one has to follow while designing a PCB, there are other important considerations applicable to the design process. Unless the PCB is designed properly in the first place, issues are going to crop up eventually. Although not complete, these considerations may be summed up as follows:

• Defining the PCB Stackup
• Introducing Suitable Via Types
• Setting Up a Breakout Strategy
• Checking Signal Integrity
• Checking Power Integrity

Defining the PCB Stackup

This is the most important step in designing a multi-layer board. As the cost of the board rises proportional to the number of its layers, specifying the stackup at the start is essential, as this defines the optimum number of layers for the PCB. This also helps the designer/engineer to establish the characteristic impedances on the various layers. In actual practice, defining the PCB stackup/layer-count is often a trade-off with the fabrication processes, through which the designer/engineer tries to achieve the desired reliability, cost targets, and yield. For the designer to understand the PCB stackup, it is necessary for them to know how manufacturers build up a multilayer PCB.

                                                    Structure of Multilayer PCB

1: Blind via. 2: Buried via. 3: Through-hole via

Image Courtesy: http://techdocs.altium.com/sites/default/files/wiki_attachments/209845/Pcb_Obj-Via_Via_LayerStackup.png

All multi-layer boards are built up of cores, pre-pregs, and copper foils in the form of a panel. The core is essentially a double-sided PCB. It consists of a rigid base laminate with copper foils pre-bonded on both sides. To make up a multi-layer PCB, manufacturers place one or more sheets of pre-preg on each side of the core, each followed by a sheet of copper foil.

In practice, the designer generates Gerber files from the PCB design software on his computer, with one set of patterns for each layer along with the drill file containing details of all the holes in that layer. The manufacturer starts with drilling the core for buried vias (if required), and electroplates them. The next step involves image transferring according to the pattern for the innermost layers, and etching the copper foils on both sides of the core. The copper patterns are usually given a chemical coating to make them suitable for bonding to subsequent layers.

Pre-pregs are formed by pre-(im)preg(nating) glass-fiber cloth with uncured resin. For the additional layers, PCB manufacturers bond sheets of copper foil and pre-preg onto the finished core using pressure and heat. The process cures the resin within the pre-preg, while bonding the panel together. The copper foils on both sides of the build are then drilled for blind vias using depth-controlled drilling machines, and the holes are electroplated. Copper pattern images for the two layers are then transferred to the panel and the sides etched. This process is repeated for all subsequent layers.

Once all the layers of the board have been built-up, the outermost copper layers also receive the same treatment of drilling for blind and through-hole vias, electroplating, image transferring, and subsequent etching. A green mask is applied to the outermost layers to prevent undesired shorting during soldering, and an application of silkscreen helps in component mounting. All exposed solderable copper pads are then given a finishing treatment as required by the customer. Finally, a routing machine separates individual boards from the panel, and cuts the PCBs to their required shape and size. Refer pcb-manufacturing-process for more details.

Introducing Suitable Via Types

With multiple layers on the PCB, there must be some way to connect between them. Designers use various types of plated through vias to interconnect the circuits on multiple layers and components. Mostly, these are Through, Buried, Blind, and Micro type vias, and each has its own function. As the name suggests, through-hole vias provide a means for mounting components with leads. These holes run through the entire stack, and connect the circuit on the topmost layer to that on the bottom layer, and to any other layer in between.

Buried vias are not visible on either surface of the PCB, as they mainly connect circuits on inner layers other than that on the top and bottom layers. Blind vias connect the circuits on the outermost layers to those on any of the inner layers. Therefore, blind vias are visible only on any one of the outermost layers.

Introduction of highly integrated packages such as the Ball Grid Array (BGA), and the shrinking outlines of modern electronic gadgets have reduced the available space for the PCB as well. To pack more circuitry within the limited space designers now use micro-vias. These are extremely small diameter vias, which are often placed on pads and tracks giving more space to the designer to route their traces. Vias placed on pads or tracks are electroplated and often filled and covered with copper.

Designers should ensure the via they have chosen to apply has the desired current carrying capacity. They can parallel additional vias to build up the necessary high current paths.

Setting Up a Breakout Strategy

The designer must ensure it is possible to breakout and route all the signals on high-pin-count integrated circuits that are so common nowadays—as this will affect the stackup of the PCB as well. This may require extensive use of micro-vias and in-pad vias that go deep into the stack. After defining the stackup, the designer must decide on the routing strategy to be used for the board—a layer-based breakout, the traditional East, West, North, and South, or a hybrid style.

Checking Signal Integrity

This is an essential part of designing a good PCB. An engineer will typically consider things such as track lengths, characteristic impedances, and the signal rise and fall times on them. He or she will also consider the drive strengths of the drivers and the resulting slew rates due to terminations. To ensure the best performance, the pre-layout and post-layout signal-integrity simulations are very useful, as is the consideration for the crosstalk budget.

Checking Power Integrity

Modern high-performing devices, especially ASICs and FPGAs, usually work on low voltages but require large currents. Therefore, considerations for the power distribution network and its static and dynamic performance on the multi-layer board assume greater significance, and defining the power and ground layers in the stackup is important to characterize this performance. Placement of the power and ground layers with respect to the signal layers also affects signal integrity, especially for traces that carry high-frequency or high-speed signals.

Conclusion

The above does not necessarily cover all aspects of the design of all types of multi-layer PCBs, but only the most important ones to provide a good starting point. For instance, designers of multi-layer PCBs for power circuits must consider wider traces to withstand higher currents, use an inner layer for control ground, and keep the power and control grounds separate.

Likewise, designers of multi-layer boards for mixed-signal circuits must consider protecting the analog ground from noise, and keep the digital and analog grounds separate.

Finally, there are two very important points every designer of multi-layer PCBs should consider. First, they should engage with a manufacturer of PCBs with proven capabilities in the field. Second, the designer should be in constant touch with their PCB provider to ensure the design they are proposing is manufacturable.

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Online PCB Specialist - PCB Power

PCBPOWER (Subsidiary of Circuit Systems India Ltd) has come a long way ever since it began to manufacture PCBs in 1996 to become one of India’s leading PCB manufacturers today. The company’s high quality and cost effective printed circuit boards with its unmatched consistency and customer-centricity has earned it respect and appreciation on a global level. PCBPOWER has a long-established reputation in providing its customers prototype and small volume through an efficient usage of the state of the art production facility.

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Url  : http://www.pcbpower.com
Email: pcb@pcbpower.com
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